1. Field of the Invention
The present invention relates to a read-only semiconductor memory device to be used as a memory device of a computer or the like. More specifically, the invention relates to a nonvolatile read-only semiconductor memory device having a floating gate, whose surface is not covered with a control gate.
2. Description of the Prior Art
Conventionally, there is a structure for a nonvolatile semiconductor device, in which two layers of gates, i.e. a floating gate and a control gate, are provided. However, such semiconductor device requires large number of fabrication process for formation of two layers of gates. Therefore, there has been proposed a nonvolatile semiconductor memory device which has a structure with only one layer of gate (Japanese Unexamined Patent Publication No. Hei 7-288291). FIG. 1A is a diagrammatic plan view of a conventional semiconductor memory device disclosed in Japanese Unexamined Patent Publication No. Hei 7-288291, and FIG. 1B is a section taken along line A--A in FIG. 1A. It should be noted that an interlayer insulation layer and an isolation oxide layer are neglected from illustration in FIG. 1A. In the shown semiconductor memory device, an n-type drain diffusion layer 111, an n-type source diffusion layer 112 and an n-type control gate diffusion layer are stacked on the surface of a p-type semiconductor substrate 110 of single crystalline silicon. Also, a p-type channel region 125 is formed between the drain diffusion layer 111 and source diffusion layer 112. An isolation oxide layer 117 is formed between the respective diffusion layers except for the channel region 125. A tunnel insulation layer 119a covering a part of the drain diffusion layer 111, a part of the source diffusion layer 112 and the channel region 125 and a tunnel insulation layer 119b covering a part of the control gate diffusion layer 114 are formed. The tunnel insulation layers 119a and 119b are integrated with each other. Also, a floating gate 113 of polycrystalline silicon is formed on the tunnel insulation layers 119a and 119b.
Also, a protective layer 118 of polycrystalline silicon is formed via an insulation layer 120 above a part of the floating gate 113. Then, the respective elements formed on or above the surface of the p-type semiconductor substrate 110 are covered with an interlayer insulation layer 126. Also, contact holes 121 to 124 are provided through the interlayer insulation later 126. Then, the drain diffusion layer 111 is connected to a drain electrode 211 of aluminum via the contact hole 121. The source diffusion layer 112 is connected to a source electrode 212 of aluminum via the contact hole 122. Also, the control gate diffusion layer 114 is connected to a control gate electrode 214 of aluminum via the contact hole 123. The protective layer 118 is connected to a protective gate electrode 218 of aluminum via the contact hole 124. The protective gate electrode 218 and the drain electrode 211 are connected to each other.
Next, operation of the foregoing semiconductor device will be discussed. FIG. 2 is a diagrammatic illustration showing an equivalent circuit of the memory cell. Some parasitic capacitance is present between the floating gate 113 and the drain diffusion layer 111, between the floating gate 113 and the source diffusion layer 112, between the floating gate 113 and the p-type semiconductor substrate 110 and between the floating gate 113 and the control gate diffusion layer 114, respectively. Each parasitic capacitance is respectively assumed as C.sub.FD, C.sub.FS, C.sub.FB and C.sub.CF in sequential order. Also, a large parasitic capacitance is present between the floating gate 113 and the protective gate 118. Since the protective gate 118 is connected to the drain electrode 211, this parasitic capacitance is included in C.sub.FD. At this time, an expression of C.sub.FD &gt;&gt;C.sub.FS, C.sub.FB and C.sub.CF exists.
The following table 1 shows potential to be applied to the memory cell upon writing or erasing.
TABLE 1 ______________________________________ DRAIN SOURCE CONTROL GATE ______________________________________ WRITING GROUND -- V.sub.PP ERASING V.sub.PP -- GROUND ______________________________________
Upon writing, as shown in the foregoing table 1, the drain electrode 211 is biased to the grounding potential, the control gate electrode 214 is biased to high potential V.sub.PP for programming, and no potential is applied to the source electrode 212. At this time, since the expression of C.sub.FD &gt;&gt;C.sub.FS, C.sub.FB and C.sub.CF exists, the potential of the floating gate 113 is biased substantially to the grounding potential as the same potential as the drain diffusion layer 111. Therefore, a potential difference between the floating gate 113 and the control gate diffusion layer 114 becomes substantially equal to V.sub.PP to cause movement of electron from the floating gate 113 to the control gate diffusion layer 114 by tunnel effect. Thus, the threshold voltage (hereinafter referred to as V.sub.tm) of the memory cell is shifted to low voltage to memorize "1", for example.
On the other hand, upon erasing, as shown in the table 1, the drain electrode 211 is biased to the high potential V.sub.PP, the control gate electrode 214 is biased to the grounding potential. Then, no potential is applied to the source electrode 212. At this time, since the expression of C.sub.FD &gt;&gt;C.sub.FS, C.sub.CB and C.sub.CF exists, the potential of the floating gate 113 is biased substantially to V.sub.PP. On the other hand, the control gate electrode 214 is biased to the grounding potential. Therefore, the potential difference between the floating gate 113 and the control gate diffusion layer 114 becomes substantially equal to V.sub.PP to cause movement of electron from the control gate diffusion layer 114 to the floating gate 113 conversely to the case of writing by the tunnel effect. Therefore, the threshold voltage V.sub.tm is shifted to high voltage to memorize "0", for example.
However, since the floating gate 113 is not completely covered with the protective gate 118 in such a semiconductor memory device, if a quite large amount of mobile ion, such as Na ion or the like, penetrates into the chip, some mobile ion may reach the floating gate 113. Therefore, electron stored up in the floating gate 113 is electrically neutralized to destroy the memorized data.
When a structure to completely cover the floating gate 113 with a protective layer is taken in order to prevent the mobile ion from penetrating, another problem should be encountered. For example, when the floating gate 113 is completely covered with the protective gate 118a and 118b as shown with chain lines in FIGS. 1A and 1B, if the insulation layer 120 is formed thinner, coupling capacitance between the protective gate 118, 118a and 180b and the floating gate 113 becomes larger. At this time, since the drain electrode 211 and the protective gate electrode 218 are connected to each other, the potential of the drain diffusion layer 111 and the potential of the floating gate 113 become substantially equal to each other. Thus, it appears that the potential difference between the control gate diffusion layer 114 and the floating gate 113 becomes closer to V.sub.PP upon writing and erasing to improve efficiency of writing and erasing. However, since the protective gate 118b and the control gate diffusion layer 114 are located adjacently, transfer of electron is caused even between the protective gate 118b and the control gate diffusion layer 114 by the tunnel effect. This transfer of electron does not contribute for writing and erasing, and the efficiency of writing and erasing is lowered practically.
On the other hand, when the insulation layer 120 is formed thicker, the coupling capacitance between the protective gates 118, 118a and 180b and the floating gate 113 becomes smaller. Therefore, the potential difference between the floating gate 113 and the control gate diffusion layer 114 becomes smaller than V.sub.PP to lower the efficiency of writing and erasing.
On the other hand, there has been proposed a nonvolatile semiconductor memory device, in which the tunnel effect between the protective gate and the control diffusion layer is prevented (Japanese Unexamined Patent Publication No. Hei 2-2684). FIG. 3A is a diagrammatic plan view of a conventional semiconductor memory device disclosed in the foregoing publication, and FIG. 3B is a section taken along line B--B in FIG. 3A. It should be noted that the interlayer insulation layer and the isolation oxide layer are ommitted from FIG. 3A. In the shown semiconductor memory device, an n-type drain diffusion layer 131, an n-type source diffusion layer 132 and an n-type control gate diffusion layer 134 are stacked on the surface of the p-type semiconductor substrate 130. Also, a p-type channel region 145 is formed between the drain diffusion layer 131 and the source diffusion layer 132. An isolation oxide layer 137 is formed between the respective diffusion layers except for the channel region 145. A tunnel insulation layer 139a covering a part of the drain diffusion layer 131, a part of the source diffusion layer 132 and the channel region 145 and a tunnel insulation layer 139b covering the control gate diffusion layer 134 and a part of the isolation layer 137 formed on both sides of the control gate diffusion layer 134 are formed. The tunnel insulation layers 139a and 139b are integrated with each other. Also, a floating gate 133 of polycrystalline silicon is formed on the tunnel insulation layers 139a and 139b. A distance between the floating gate 133 and a portion of the drain diffusion layer 131 is narrower than a distance between the floating gate 133 and the source diffusion layer 132.
Also, the floating gate 133 is completely covered with a protective gate 138 of polycrystalline silicon via an insulation layer 140. The respective elements formed on or above the surface of the p-type semiconductor substrate 130 are covered with the interlayer insulation layer 146. Contact holes 141, 142 and 144 are provided through the interlayer insulation layer 146. The drain diffusion layer 131 is connected to a drain electrode 231 of aluminum via the contact hole 141, and the source diffusion layer 132 is connected to a source electrode 232 of aluminum via the contact hole 142. Also, the protective gate 138 is connected to a protective gate electrode 238 of aluminum via the contact hole 144. Then, the control gate diffusion layer 134 per se serves as the electrode 234 for the control gate.
Next, operation of the foregoing semiconductor device will be discussed. FIG. 4 is a diagrammatic illustration of an equivalent circuit of the memory cell. Some parasitic capacitance is present between the floating gate 133 and the drain diffusion layer 131, between the floating gate and the source diffusion layer 132, between the floating gate 133 and the p-type semiconductor substrate 130, between the floating gate 133 and the control gate diffusion layer 134 and between the floating gate 133 and the protective gate 138, respectively. Each parasitic capacitance is respectively assumed as C.sub.FD, C.sub.FS, C.sub.FB, C.sub.CF and C.sub.FG in sequential order. At this time an expression of C.sub.CF &gt;&gt;C.sub.FD, C.sub.FS, C.sub.FB and C.sub.FG exists.
The following table 2 shows potential to be applied to the memory cell upon writing or erasing.
TABLE 2 ______________________________________ DRAIN SOURCE CONTROL GATE ______________________________________ WRITING V.sub.PP -- GROUND ERASING GROUND -- V.sub.PP ______________________________________
Upon writing, as shown in the foregoing table 2, the drain electrode 231 is biased to high potential V.sub.PP for programming, and the control gate 234 is biased to the grounding potential. Then, no potential is applied to the source electrode 232. At this time, the potential V.sub.FGw of the floating gate 133 upon writing is expressed as the following equation (1): EQU V.sub.FGw =(C.sub.FD /(C.sub.FD +C.sub.FS +C.sub.FB +C.sub.FG +C.sub.CF)).times.V.sub.PP ( 1)
Then, since the expression of C.sub.CF &gt;&gt;C.sub.FD, C.sub.FS, C.sub.FB and C.sub.FG exists, upon writing, V.sub.FGw becomes substantially equal to 0 V. Therefore, a potential difference between the floating gate 133 and the drain diffusion layer 131 becomes substantially equal to V.sub.PP to cause movement of electron from the floating gate 133 to the drain diffusion layer 131 by the tunnel effect. Thus, the threshold voltage V.sub.tm is shifted to low voltage to memorize "1", for example.
On the other hand, upon erasing, as shown in the foregoing table 2, the drain electrode 231 is biased to the grounding potential, and the control gate electrode 243 is biased to the high potential V.sub.PP for programming. Then, no potential is applied to the source electrode 232. At this time, the potential V.sub.FGe of floating gate 133 upon erasing is expressed as the following equation (2): EQU V.sub.FGe =(C.sub.CF /(C.sub.FD +C.sub.FS +C.sub.FB +C.sub.FG +C.sub.CF)).times.V.sub.PP ( 2)
Then, the expression of C.sub.CF &gt;&gt;C.sub.FD, C.sub.FS, C.sub.FB and C.sub.FG exists, upon erasing, V.sub.FGe becomes substantially equal to V.sub.PP. Therefore, a potential difference between the floating gate 133 and the drain diffusion layer 131 becomes close to V.sub.PP. Conversely to the case of writing, electron moves from the drain diffusion layer 131 to the floating gate 133. Thus, the threshold voltage V.sub.tm is shifted to high voltage to memorize "0", for example.
However, in the shown semiconductor device, the protective gate 138 is biased to the grounding potential and parasitic capacitance C.sub.FG is present. Therefore, upon erasing, the potential of the floating gate 133 becomes much lower than V.sub.PP to lower the efficiency of erasing.
On the other hand, there has also been proposed a nonvolatile semiconductor device having a non-transparent material, such as aluminum, in order to avoid influence of light to a charge stored up in a floating gate (Japanese Unexamined Patent Publication No. Sho 63-157480). FIG. 5A is a diagrammatic plan view of a conventional semiconductor memory device disclosed in the foregoing publication, and FIG. 5B is a section taken along line C--C in FIG. 5A. It should be noted that the interlayer insulation layer and the isolation oxide layer are neglected from illustration in FIG. 5A. In the shown semiconductor memory device, an n-type drain diffusion layer 151, an n-type source diffusion layer 152 and mutually adjacent an n-type control gate diffusion layer 154 and a p-type control gate diffusion layer 155 are stacked on the surface of the p-type semiconductor substrate 150. Also, a p-type channel region 165 is formed between the drain diffusion layer 151 and the source diffusion layer 152. Also, a p-type diffusion layer 158 surrounding the foregoing elements is formed. An n-type diffusion layer 157a is formed outside of the p-type diffusion layer 158 with respect to the drain diffusion layer 151. An n-type diffusion layer 157b is formed outside of the p-type diffusion layer 158 with respect to the source diffusion layer 152. An n-type diffusion layer 157c is formed outside of the p-type diffusion layer 158 with respect to the control gate diffusion layers 154 and 155. Also, an isolation oxide layer 159 is formed between the respective diffusion layers except for the channel region 165. Then, a tunnel insulation layer 160 covering a part of the drain diffusion layer 151, a part of the source diffusion layer 152 and a part of the control gate diffusion layers 154 and 155 is formed. Furthermore, a floating gate 153 formed of polycrystalline silicon is provided on the tunnel insulation layer 160.
Also, the respective elements formed on or above the surface of the p-type semiconductor substrate 150 are covered with an interlayer insulation layer 166. Contact holes 161 to 164 reaching the n-type diffusion layers 157a, 157b or 157c or the p-type diffusion layer 158 are provided through the interlayer insulation layer 166. Furthermore, an n-type well 156a extending from the n-type diffusion layer 157a to the drain diffusion layer 151 through a portion of the p-type semiconductor substrate 150 is formed. An n-type well 156b extending from the n-type diffusion layer 157b to the source diffusion layer 152 through a portion of the p-type semiconductor substrate 150 is formed. An n-type well 156c extending from the n-type diffusion layer 157c to the control gate diffusion layers 154 and 155 through a portion of the p-type semiconductor substrate 150 and completely surrounding the control gate diffusion layers 154 and 155 is formed. The drain diffusion layer 151 is connected to a drain electrode 251 via the n-type well 156a, the n-type diffusion layer 157a and the contact hole 161. The source diffusion layer 152 is connected to a source electrode 252 via the n-type well 156b, the n-type diffusion layer 157b and the contact hole 162. Also, the control gate diffusion layers 154 and 155 are connected to a control gate electrode 254 via the n-type well 156c, the n-type diffusion layer 157c and the contact hole 163.
Then, a non-transparent material 170, such as aluminum or the like, is buried in the contact hole 164 reaching the p-type diffusion layer 158. Also, the non-transparent material 170 is stacked on the upper surface of the interlayer insulation layer 166 surrounded by the contact hole 164 to be integrated with the non-transparent material 170 buried in the contact hole 164.
Next, operation of the foregoing semiconductor device will be discussed. The following table 3 shows potential to be applied to the memory cell upon writing.
TABLE 3 ______________________________________ DRAIN SOURCE CONTROL GATE ______________________________________ WRITING HV GROUND V.sub.PP ______________________________________
Upon writing, as shown in the foregoing table 3, the drain electrode 251 is biased to high potential HV for programming, the source electrode is biased to the grounding potential and the control gate electrode 254 is biased to V.sub.PP. For example, HV is equal to 6V and V.sub.PP is equal to 12.5V. At this time, a current flows from the drain electrode 251 to the source electrode 252 to induce hot electron in the vicinity of the drain diffusion layer 151. The hot electron is injected into the floating gate 153 to shift the threshold voltage V.sub.tm to high voltage to memorize "0", for example.
On the other hand, upon erasing, irradiating ultraviolet ray to the memory cell is performed, and whereby electron stored up in the floating gate 153 is eliminated. However, since the semiconductor device is covered with the non-transparent material 170, erasing cannot be performed in the shown structure.
In this semiconductor device, the non-transparent material 170 is connected to the semiconductor substrate 150 via the p-type diffusion layer 158 and the n-type diffusion layers 156a, 156b and 156c. Since the semiconductor substrate 150 is biased to the grounding potential, the non-transparent material 170 is also connected to the grounding potential. Thus, parasitic capacitance is present between the non-transparent material 170 and the floating gate 153 to lower the potential of the floating gate 153 upon writing. Therefore, writing efficiency may be lowered.